Gate driver topologies, concepts and challenges for Wide BandGap devices
Wide BandGap (WBG) power semiconductor devices have already made a significant impact in power converters: SiC MOSFETs, unipolar devices, have reached similar conduction losses as Si IGBTs, bipolar devices, with a smaller required device area, and with much smaller switching losses, for the same breakdown voltage (BV > 650 V). GaN devices are also outperforming Silicon MOSFETs in the 100 V- 650 V class, albeit their lateral architecture compared to vertical Silicon devices. Although power semiconductor devices with better figures of merit are expected to have a positive impact at the power converter level, the appropriate and dedicated gate driving techniques are needed: the performances of WBG Field Effect Transistors (FETs) are strongly related to their gate drivers, within the power commutation cell and multicellular power converters.
In this short course, I will first detail the specificities of WBG FETs devices and their impact on gate driver topologies. I will explain the interactions and constraints between gate driver, WBG power transistor and commutation cell. The trade-offs will be described, such as EMI—losses, parameters affecting dv/dt and di/dt, active gate driving, and examples from state of the art gate drivers associated with SiC and GaN power transistors. The architectures of gate drivers and their evolutions for WBG devices will be detailed. Then, I will highlight the major gate driver concepts and challenges, from dead time control to precise timing and isolation: while digital control is now widely available, with digital clocks above several GHz and timing resolutions well below 1 ns, the specific timing challenges will be illustrated. Other important topics which are pushed forward by WBG devices will be addressed, such as gate driver supply isolation, gate signals isolation, short circuit detection and protection, integration limits and many other key challenges and upcoming opportunities specific to WBG power devices and their associated gate drivers.
Nicolas Rouger
B.E.Eng’02 (ENS, Univ. Paris-Sud Orsay, France) M.E.Eng ’05 & PhD.’08 (Grenoble Institute of Technology, France), Habil.’15, is CNRS senior scientist and group leader (Laplace Lab, Toulouse). While supervising 51 students, he contributed to more than 30 tape outs, in Silicon CMOS & power technologies, GaN and Diamond, advancing the frontiers of integration, gate drivers and power semiconductor devices. Dissemination within IEEE ISPSD (2006-2024) includes CMOS integrated ultra-fast short circuit detection and feedback loop for dv/dt control, optical gate driver (analog, digital and power), and more.